1. The Field of the Invention
The present invention relates to a metallized integrated circuit structure, and particularly to a metallized interconnect structure situated on a semiconductor substrate assembly and methods for making.
2. The Relevant Technology
Current technology for metallization of an integrated circuit involves the forming of a conductive layer over the integrated circuit. A typical metallization process is one that is performed at the “back end of the line,” which is after the formation of integrated circuits that are to be wired by the metallization process. A single conductive layer is often formed so that it is situated above the integrated circuit to be wired. After the conductive layer is formed, it is then patterned and etched into a shape of the desired wiring necessary to metallize the integrated circuit. Since the conductive layer is situated above the integrated circuit, the resultant metallization will also be above the integrated circuit in a “wiring-up” scheme.
Another type of metallization involves the formation of a conductive layer at least in part below the integrated circuit in a recess composed of an electrically insulative or dielectric material. Such a wiring scheme may be described as a “wiring-down” scheme. The recess can be either a trench, a hole, or a via. Depending upon the aspect ratio of the recess, poor step coverage of the conductive layer within the recess may result. Voids in the conductive layer within the recess may also result when the conductive layer does not completely fill up the recess. Voids and poor step coverage can cause the integrated circuit to experience an electrical failure. The electrical failure can be experienced during fabrication of the integrated circuit or after a period of time that the integrated circuit has been in use, such as where electrical contact with the conductive layer in the recess has been lost because the material of the conductive layer moves.
It would be an advantage in the art to overcome the problems of poor step coverage and voids.